CURRICULUM VITAE
Education
PHD IN ELECTRICAL ENGINEERING, GEORGIA INSTITUTE OF TECHNOLOGY
August 2018 - Present
Areas of Research
- Clock Networks for 2.5D Integrated Systems​​​
- Heterogeneous Monolithic/F2F 3D IC Design for Near-memory and In-memory ML Accelerators
- True 3D Placement Tools for 3D ICs
Minor: Computer Science
Grade: 3.9/4.0
MS IN ELECTRICAL ENGINEERING,
GEORGIA INSTITUTE OF TECHNOLOGY
Specializations
- Very Large Scale Integration (VLSI)
- Computer Systems
Grade: 4.0/4.0
Aug 2018 - May 2020
BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION,
PSG COLLEGE OF TECHNOLOGY
Gold Medalist
Best Outgoing Student of Department of Electronics and Communication
Grade: 9.66/10.0
Jul 2012 - May 2016
Professional Experience
GRADUATE INTERIM INTERN, QUALCOMM
1. 3D SoC-level Netlist partitioner using C++ for a commercial IP.
Jun 2022 - Aug 2022
GRADUATE TECHNICAL INTERN, INTEL
1. Scaling accelerator hardware through 3D architecture and design space exploration to meet the compute and memory demands of future workloads.
2. Synthesis and APR of the digital blocks in a resonant clocking system prototype.
Jan 2021 - Aug 2021
HARDWARE ENGINEERING INTERN, APPLE
1. Researched on ways to improve the wirelength optimization in a latest commercial PDK during the physical design of a commercial IP
May 2021 - Aug 2021
SOC DESIGN ENGINEER, INTEL
Jul 2016 - Jul 2018
RTL Design of DDR IO IP
Clock Domain Crossing Verification
Analog and Mixed-Signal Verification
UNDERGRAD INTERN, INTEL
Dec 2015 - Jun 2016
RTL Design of PCI Express IP
Linting
UPF Analysis
TEACHING STAFF, NIIT TECHNOLOGIES PVT LTD
C Programming Tutor for college students and working professionals
Sep 2013 - Nov 2013
Technical Skills
LANGUAGES
System Verilog, C, C++, TCL, Bash, Python, MATLAB
TOOLS AND UTILITIES
SpyglassCDC, Cadence Innovus, Synopsys ICC2, Synopsys Design Compiler, Cadence SiP, Synopsys VCS, Synopsys Verdi, SpyglassDFT
OPERATING SYSTEMS
Unix, Linux, Windows, MacOS